Field of the Disclosure
The present disclosure relates to a memory device, and in particular, it relates to a resistive random access memory (RRAM).
Description of the Related Art
Designers are now looking at next-generation nonvolatile memories such as magnetoresistive random access memories (MRAMs), phase change random access Memories (PCRAMs), conductive bridging random access memories (CBRAMs) and resistive random access memories (RRAMs), to increase writing speeds and decrease power consumption. Among the non-volatile memories, the RRAM has become a mainstream option for emerging non-volatile memories due to its simple structure, simple crossbar array, suitability for low-temperature fabrication, low power consumption, low operating voltage, short writing/erasing times, long endurance, long retention times, non-destructive read, multi-state memory, simple device fabrication and capability of microminiaturizing. A conventional resistive non-volatile memory cell structure is composed of a bottom electrode, a resistive switching layer, and a top electrode to constitute a stack of metal-insulator-metal (MIM). Moreover, the resistive switching (RS) property of resistive non-volatile memory is important for devices.
Although the RRAM crossbar array architecture is simple, there are still many problems that need to be overcome for fabrication, especially for three-dimensional (3D) crossbar array architectures. Without a vertical 3D architecture, the RRAM will most likely not be able to compete with 3D NAND memories in terms of bit cost for mass data storage.
The RRAM crossbar array architectures based on resistive switching elements theoretically allows for the smallest cell size of 4F2 where F is the minimum feature size, and the low-temperature fabrication enables stacking of memory arrays three-dimensionally, for unprecedented high-integration density. However, in the 1R structure (having a resistive element only), undesired sneak current that flows through neighboring unselected memory cells significantly deteriorates the read margin, and limits the maximum size of the crossbar array to below 64 bits. This problem can be mitigated by additional non-linear selection devices in series with the resistive switching elements. Some memory cell structures, such as one diode-one resistor (1D1R), one bipolar selector-one resistor (1S1R), one MOSFET transistor-one resistor (1T1R), and one bipolar junction transistor-one resistor 1BJT1R memory cell structures, have been developed. Among the memory cell structures, the 1T1R and 1BJT1R memory cell structures are undesirable because of the complicated and high-temperature fabrication requirements of MOSFETs and BJTs, while the complementary resistive switching (CRS) memory cell structure suffers from the issue of destructive read. Hence, the 1D1R and 1S1R memory cell structures appear to be the leading contenders for the 3D crossbar array architectures.